Phase lock loops commonly have been utilized in communication devices for generating signals phase locked to a reference frequency. For example, a dual-conversion receiver needs two injection signals that are not necessarily harmonically related. Similarly, a transceiver, which might include the dual conversion receiver, may need a third frequency for exciting the transmitter. In addition, a microprocessor that is used for processing radio signals of the transceiver may need yet another frequency as a clock signal for general operation.
In the past, multiple signals that were not harmonically related typically have required multiple phase lock loops. These implementations have required multiple external reference oscillators, which have been costly and have affected manufacturing quality of communication devices. Moreover, multiple phase lock loops consume power and integrated circuit (IC) real estate. Portable communication devices that are battery operated are adversely affected as to battery life, by utilizing a plurality of independent phase lock loops.
Thus, whenever multiple phase lock loops are required, it is desirable to combine portions of the multiple phase lock loops, where possible, to reduce power consumption and to minimize IC real estate. What is needed, then, is a frequency synthesizer for generating a plurality of signals operating at a plurality of frequencies. In particular, the frequency synthesizer should consume less power, and use less IC real estate than prior art frequency synthesizers using multiple phase lock loops.